Bit18, Error occurred in data translation cache.
Bit16, Error occurred in the data translation registers.
Bit19, Error occurred in the instruction translation cache.
Bit17, Error occurred in the instruction translation registers
Bit23:20, Type of cache operation that caused the machine check: 0 - unknown 1 - TLB access due to load instruction 2 - TLB access due to store instruction 3 - TLB access due to instruction fetch or instruction prefetch 4 - TLB access due to data prefetch (both hardware and software) 5 - TLB shoot down access 6 - TLB probe instruction (probe, tpa) 7 - move in (VHPT fill) 8 - purge (insert operation that purges entries or a TLB purge instruction) All other values are reserved.
Bit7:0, Slot number of the translation register where the failure occurred.
Bit8, The tr_slot field in the TLB_check parameter is valid.
Bit54, Instruction set. If this value is set to zero, the instruction that generated the machine check was an Intel Itanium instruction. If this bit is set to one, the instruction that generated the machine check was IA-32 instruction.
Bit55, The is field in the TLB_check parameter is valid.
Bit59, Machine check corrected: This bit is set to one to indicate that the machine check has been corrected.
Bit63 Precise instruction pointer. This bit is set to one to indicate that a valid precise instruction pointer has been logged.
Bit57:56, Privilege level. The privilege level of the instruction bundle responsible for generating the machine check.
Bit58, The pl field of the TLB_check parameter is valid.
Bit61 Requester identifier: This bit is set to one to indicate that a valid requester identifier has been logged.
Bit62, Responder identifier: This bit is set to one to indicate that a valid responder identifier has been logged.
Bit60, Target address is valid: This bit is set to one to indicate that a valid target address has been logged.
Bit11:10, The level of the TLB where the error occurred. A value of 0 indicates the first level of TLB