Defines | |
#define | ASSERT_INVALID_PCI_ADDRESS(A, M) ASSERT (((A) & (~0xfffffff | (M))) == 0) |
#define | CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address) ((((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff)) |
#define | CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address) (Address) |
#define | IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0) |
Functions | |
UINT32 | DxePciLibEsalReadWorker (IN UINTN Address, IN UINTN Width) |
UINT32 | DxePciLibEsalWriteWorker (IN UINTN Address, IN UINTN Width, IN UINT32 Data) |
RETURN_STATUS EFIAPI | PciRegisterForRuntimeAccess (IN UINTN Address) |
UINT8 EFIAPI | PciRead8 (IN UINTN Address) |
UINT8 EFIAPI | PciWrite8 (IN UINTN Address, IN UINT8 Data) |
UINT8 EFIAPI | PciOr8 (IN UINTN Address, IN UINT8 OrData) |
UINT8 EFIAPI | PciAnd8 (IN UINTN Address, IN UINT8 AndData) |
UINT8 EFIAPI | PciAndThenOr8 (IN UINTN Address, IN UINT8 AndData, IN UINT8 OrData) |
UINT8 EFIAPI | PciBitFieldRead8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit) |
UINT8 EFIAPI | PciBitFieldWrite8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 Value) |
UINT8 EFIAPI | PciBitFieldOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 OrData) |
UINT8 EFIAPI | PciBitFieldAnd8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData) |
UINT8 EFIAPI | PciBitFieldAndThenOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData, IN UINT8 OrData) |
UINT16 EFIAPI | PciRead16 (IN UINTN Address) |
UINT16 EFIAPI | PciWrite16 (IN UINTN Address, IN UINT16 Data) |
UINT16 EFIAPI | PciOr16 (IN UINTN Address, IN UINT16 OrData) |
UINT16 EFIAPI | PciAnd16 (IN UINTN Address, IN UINT16 AndData) |
UINT16 EFIAPI | PciAndThenOr16 (IN UINTN Address, IN UINT16 AndData, IN UINT16 OrData) |
UINT16 EFIAPI | PciBitFieldRead16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit) |
UINT16 EFIAPI | PciBitFieldWrite16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 Value) |
UINT16 EFIAPI | PciBitFieldOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 OrData) |
UINT16 EFIAPI | PciBitFieldAnd16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData) |
UINT16 EFIAPI | PciBitFieldAndThenOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData, IN UINT16 OrData) |
UINT32 EFIAPI | PciRead32 (IN UINTN Address) |
UINT32 EFIAPI | PciWrite32 (IN UINTN Address, IN UINT32 Data) |
UINT32 EFIAPI | PciOr32 (IN UINTN Address, IN UINT32 OrData) |
UINT32 EFIAPI | PciAnd32 (IN UINTN Address, IN UINT32 AndData) |
UINT32 EFIAPI | PciAndThenOr32 (IN UINTN Address, IN UINT32 AndData, IN UINT32 OrData) |
UINT32 EFIAPI | PciBitFieldRead32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit) |
UINT32 EFIAPI | PciBitFieldWrite32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value) |
UINT32 EFIAPI | PciBitFieldOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 OrData) |
UINT32 EFIAPI | PciBitFieldAnd32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData) |
UINT32 EFIAPI | PciBitFieldAndThenOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData, IN UINT32 OrData) |
UINTN EFIAPI | PciReadBuffer (IN UINTN StartAddress, IN UINTN Size, OUT VOID *Buffer) |
UINTN EFIAPI | PciWriteBuffer (IN UINTN StartAddress, IN UINTN Size, IN VOID *Buffer) |
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define ASSERT_INVALID_PCI_ADDRESS | ( | A, | |||
M | ) | ASSERT (((A) & (~0xfffffff | (M))) == 0) |
Assert the validity of a PCI address. A valid PCI address should contain 1's only in the low 28 bits.
A | The address to validate. | |
M | Additional bits to assert to be zero. |
#define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 | ( | Address | ) | ((((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff)) |
Converts a PCI Library Address to a ESAL PCI Service Address. Based on SAL Spec 3.2, there are two SAL PCI Address:
If address type = 0 Bits 0..7 - Register address Bits 8..10 - Function number Bits 11..15 - Device number Bits 16..23 - Bus number Bits 24..31 - PCI segment group Bits 32..63 - Reserved (0)
If address type = 1 Bits 0..7 - Register address Bits 8..11 - Extended Register address Bits 12..14 - Function number Bits 15..19 - Device number Bits 20..27 - Bus number Bits 28..43 - PCI segment group Bits 44..63 - Reserved (0)
A | The PCI Library Address to convert. |
Referenced by DxePciLibEsalReadWorker(), and DxePciLibEsalWriteWorker().
#define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 | ( | Address | ) | (Address) |
Referenced by DxePciLibEsalReadWorker(), and DxePciLibEsalWriteWorker().
#define IS_PCI_COMPATIBLE_ADDRESS | ( | Address | ) | (((Address) & 0xf00) == 0) |
Check a PCI Library Address is a PCI Compatible Address or not.
Referenced by DxePciLibEsalReadWorker(), DxePciLibEsalWriteWorker(), DxePciSegmentLibEsalReadWorker(), and DxePciSegmentLibEsalWriteWorker().
UINT32 DxePciLibEsalReadWorker | ( | IN UINTN | Address, | |
IN UINTN | Width | |||
) |
Internal worker function to read a PCI configuration register.
This function wraps EsalPciConfigRead function of Extended SAL PCI Services Class. It reads and returns the PCI configuration register specified by Address, the width of data is specified by Width.
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
Width | Width of data to read |
References CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0, CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1, EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI, EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO, EFI_SAL_PCI_COMPATIBLE_ADDRESS, EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS, EsalCall(), IS_PCI_COMPATIBLE_ADDRESS, SAL_RETURN_REGS::r9, and SalPciConfigReadFunctionId.
Referenced by PciRead16(), PciRead32(), and PciRead8().
Internal worker function to writes a PCI configuration register.
This function wraps EsalPciConfigWrite function of Extended SAL PCI Services Class. It writes the PCI configuration register specified by Address with the value specified by Data. The width of data is specifed by Width. Data is returned.
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
Width | Width of data to write | |
Data | The value to write. |
References CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0, CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1, EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI, EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO, EFI_SAL_PCI_COMPATIBLE_ADDRESS, EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS, EsalCall(), IS_PCI_COMPATIBLE_ADDRESS, and SalPciConfigWriteFunctionId.
Referenced by PciWrite16(), PciWrite32(), and PciWrite8().
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. |
References PciRead16(), and PciWrite16().
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. |
References PciRead32(), and PciWrite32().
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. |
References PciRead8(), and PciWrite8().
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References PciRead16(), and PciWrite16().
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References PciRead32(), and PciWrite32().
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References PciRead8(), and PciWrite8().
UINT16 EFIAPI PciBitFieldAnd16 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | AndData | |||
) |
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 16-bit register.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
AndData | The value to AND with the PCI configuration register. |
References BitFieldAnd16(), PciRead16(), and PciWrite16().
UINT32 EFIAPI PciBitFieldAnd32 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | AndData | |||
) |
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
AndData | The value to AND with the PCI configuration register. |
References BitFieldAnd32(), PciRead32(), and PciWrite32().
UINT8 EFIAPI PciBitFieldAnd8 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | AndData | |||
) |
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
AndData | The value to AND with the PCI configuration register. |
References BitFieldAnd8(), PciRead8(), and PciWrite8().
UINT16 EFIAPI PciBitFieldAndThenOr16 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | AndData, | |||
IN UINT16 | OrData | |||
) |
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References BitFieldAndThenOr16(), PciRead16(), and PciWrite16().
UINT32 EFIAPI PciBitFieldAndThenOr32 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | AndData, | |||
IN UINT32 | OrData | |||
) |
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References BitFieldAndThenOr32(), PciRead32(), and PciWrite32().
UINT8 EFIAPI PciBitFieldAndThenOr8 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | AndData, | |||
IN UINT8 | OrData | |||
) |
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References BitFieldAndThenOr8(), PciRead8(), and PciWrite8().
UINT16 EFIAPI PciBitFieldOr16 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | OrData | |||
) |
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
OrData | The value to OR with the PCI configuration register. |
References BitFieldOr16(), PciRead16(), and PciWrite16().
UINT32 EFIAPI PciBitFieldOr32 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | OrData | |||
) |
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
OrData | The value to OR with the PCI configuration register. |
References BitFieldOr32(), PciRead32(), and PciWrite32().
UINT8 EFIAPI PciBitFieldOr8 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | OrData | |||
) |
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
OrData | The value to OR with the PCI configuration register. |
References BitFieldOr8(), PciRead8(), and PciWrite8().
Reads a bit field of a PCI configuration register.
Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
Address | PCI configuration register to read. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. |
References BitFieldRead16(), and PciRead16().
Reads a bit field of a PCI configuration register.
Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
Address | PCI configuration register to read. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. |
References BitFieldRead32(), and PciRead32().
Reads a bit field of a PCI configuration register.
Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
Address | PCI configuration register to read. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. |
References BitFieldRead8(), and PciRead8().
UINT16 EFIAPI PciBitFieldWrite16 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | Value | |||
) |
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
Value | New value of the bit field. |
References BitFieldWrite16(), PciRead16(), and PciWrite16().
UINT32 EFIAPI PciBitFieldWrite32 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | Value | |||
) |
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
Value | New value of the bit field. |
References BitFieldWrite32(), PciRead32(), and PciWrite32().
UINT8 EFIAPI PciBitFieldWrite8 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | Value | |||
) |
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
Value | New value of the bit field. |
References BitFieldWrite8(), PciRead8(), and PciWrite8().
Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
OrData | The value to OR with the PCI configuration register. |
References PciRead16(), and PciWrite16().
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
OrData | The value to OR with the PCI configuration register. |
References PciRead32(), and PciWrite32().
Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
OrData | The value to OR with the PCI configuration register. |
References PciRead8(), and PciWrite8().
Reads a 16-bit PCI configuration register.
Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. |
References ASSERT_INVALID_PCI_ADDRESS, and DxePciLibEsalReadWorker().
Reads a 32-bit PCI configuration register.
Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. |
References ASSERT_INVALID_PCI_ADDRESS, and DxePciLibEsalReadWorker().
Reads an 8-bit PCI configuration register.
Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. |
References ASSERT_INVALID_PCI_ADDRESS, and DxePciLibEsalReadWorker().
UINTN EFIAPI PciReadBuffer | ( | IN UINTN | StartAddress, | |
IN UINTN | Size, | |||
OUT VOID * | Buffer | |||
) |
Reads a range of PCI configuration registers into a caller supplied buffer.
Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.
If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().
StartAddress | Starting address that encodes the PCI Bus, Device, Function and Register. | |
Size | Size in bytes of the transfer. | |
Buffer | Pointer to a buffer receiving the data read. |
References ASSERT, ASSERT_INVALID_PCI_ADDRESS, NULL, PciRead16(), PciRead32(), and PciRead8().
RETURN_STATUS EFIAPI PciRegisterForRuntimeAccess | ( | IN UINTN | Address | ) |
Register a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap().
If Address > 0x0FFFFFFF, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. |
RETURN_SUCCESS | The PCI device was registered for runtime access. | |
RETURN_UNSUPPORTED | An attempt was made to call this function after ExitBootServices(). | |
RETURN_UNSUPPORTED | The resources required to access the PCI device at runtime could not be mapped. | |
RETURN_OUT_OF_RESOURCES | There are not enough resources available to complete the registration. |
References ASSERT_INVALID_PCI_ADDRESS, and RETURN_SUCCESS.
Writes a 16-bit PCI configuration register.
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
Data | The value to write. |
References ASSERT_INVALID_PCI_ADDRESS, and DxePciLibEsalWriteWorker().
Writes a 32-bit PCI configuration register.
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
Data | The value to write. |
References ASSERT_INVALID_PCI_ADDRESS, and DxePciLibEsalWriteWorker().
Writes an 8-bit PCI configuration register.
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | Address that encodes the PCI Bus, Device, Function and Register. | |
Data | The value to write. |
References ASSERT_INVALID_PCI_ADDRESS, and DxePciLibEsalWriteWorker().
UINTN EFIAPI PciWriteBuffer | ( | IN UINTN | StartAddress, | |
IN UINTN | Size, | |||
IN VOID * | Buffer | |||
) |
Copies the data in a caller supplied buffer to a specified range of PCI configuration space.
Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.
If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().
StartAddress | Starting address that encodes the PCI Bus, Device, Function and Register. | |
Size | Size in bytes of the transfer. | |
Buffer | Pointer to a buffer containing the data to write. |
References ASSERT, ASSERT_INVALID_PCI_ADDRESS, NULL, PciWrite16(), PciWrite32(), and PciWrite8().