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PCI_BRIDGE_CONTROL_REGISTER Struct Reference
Data Fields
UINT32
Bar
[2]
UINT8
PrimaryBus
UINT8
SecondaryBus
UINT8
SubordinateBus
UINT8
SecondaryLatencyTimer
UINT8
IoBase
UINT8
IoLimit
UINT16
SecondaryStatus
UINT16
MemoryBase
UINT16
MemoryLimit
UINT16
PrefetchableMemoryBase
UINT16
PrefetchableMemoryLimit
UINT32
PrefetchableBaseUpper32
UINT32
PrefetchableLimitUpper32
UINT16
IoBaseUpper16
UINT16
IoLimitUpper16
UINT8
CapabilityPtr
UINT8
Reserved
[3]
UINT32
ExpansionRomBAR
UINT8
InterruptLine
UINT8
InterruptPin
UINT16
BridgeControl
Detailed Description
PCI-PCI Bridge header region in PCI Configuration Space Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
Field Documentation
UINT32
PCI_BRIDGE_CONTROL_REGISTER::Bar
[2]
UINT16
PCI_BRIDGE_CONTROL_REGISTER::BridgeControl
UINT8
PCI_BRIDGE_CONTROL_REGISTER::CapabilityPtr
UINT32
PCI_BRIDGE_CONTROL_REGISTER::ExpansionRomBAR
UINT8
PCI_BRIDGE_CONTROL_REGISTER::InterruptLine
UINT8
PCI_BRIDGE_CONTROL_REGISTER::InterruptPin
UINT8
PCI_BRIDGE_CONTROL_REGISTER::IoBase
UINT16
PCI_BRIDGE_CONTROL_REGISTER::IoBaseUpper16
UINT8
PCI_BRIDGE_CONTROL_REGISTER::IoLimit
UINT16
PCI_BRIDGE_CONTROL_REGISTER::IoLimitUpper16
UINT16
PCI_BRIDGE_CONTROL_REGISTER::MemoryBase
UINT16
PCI_BRIDGE_CONTROL_REGISTER::MemoryLimit
UINT32
PCI_BRIDGE_CONTROL_REGISTER::PrefetchableBaseUpper32
UINT32
PCI_BRIDGE_CONTROL_REGISTER::PrefetchableLimitUpper32
UINT16
PCI_BRIDGE_CONTROL_REGISTER::PrefetchableMemoryBase
UINT16
PCI_BRIDGE_CONTROL_REGISTER::PrefetchableMemoryLimit
UINT8
PCI_BRIDGE_CONTROL_REGISTER::PrimaryBus
UINT8
PCI_BRIDGE_CONTROL_REGISTER::Reserved
[3]
UINT8
PCI_BRIDGE_CONTROL_REGISTER::SecondaryBus
UINT8
PCI_BRIDGE_CONTROL_REGISTER::SecondaryLatencyTimer
UINT16
PCI_BRIDGE_CONTROL_REGISTER::SecondaryStatus
UINT8
PCI_BRIDGE_CONTROL_REGISTER::SubordinateBus
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