MdePkg/Include/Library/PciCf8Lib.h File Reference


Defines

#define PCI_CF8_LIB_ADDRESS(Bus, Device, Function, Offset)   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))

Functions

RETURN_STATUS EFIAPI PciCf8RegisterForRuntimeAccess (IN UINTN Address)
UINT8 EFIAPI PciCf8Read8 (IN UINTN Address)
UINT8 EFIAPI PciCf8Write8 (IN UINTN Address, IN UINT8 Value)
UINT8 EFIAPI PciCf8Or8 (IN UINTN Address, IN UINT8 OrData)
UINT8 EFIAPI PciCf8And8 (IN UINTN Address, IN UINT8 AndData)
UINT8 EFIAPI PciCf8AndThenOr8 (IN UINTN Address, IN UINT8 AndData, IN UINT8 OrData)
UINT8 EFIAPI PciCf8BitFieldRead8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
UINT8 EFIAPI PciCf8BitFieldWrite8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 Value)
UINT8 EFIAPI PciCf8BitFieldOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 OrData)
UINT8 EFIAPI PciCf8BitFieldAnd8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData)
UINT8 EFIAPI PciCf8BitFieldAndThenOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData, IN UINT8 OrData)
UINT16 EFIAPI PciCf8Read16 (IN UINTN Address)
UINT16 EFIAPI PciCf8Write16 (IN UINTN Address, IN UINT16 Value)
UINT16 EFIAPI PciCf8Or16 (IN UINTN Address, IN UINT16 OrData)
UINT16 EFIAPI PciCf8And16 (IN UINTN Address, IN UINT16 AndData)
UINT16 EFIAPI PciCf8AndThenOr16 (IN UINTN Address, IN UINT16 AndData, IN UINT16 OrData)
UINT16 EFIAPI PciCf8BitFieldRead16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
UINT16 EFIAPI PciCf8BitFieldWrite16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 Value)
UINT16 EFIAPI PciCf8BitFieldOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 OrData)
UINT16 EFIAPI PciCf8BitFieldAnd16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData)
UINT16 EFIAPI PciCf8BitFieldAndThenOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData, IN UINT16 OrData)
UINT32 EFIAPI PciCf8Read32 (IN UINTN Address)
UINT32 EFIAPI PciCf8Write32 (IN UINTN Address, IN UINT32 Value)
UINT32 EFIAPI PciCf8Or32 (IN UINTN Address, IN UINT32 OrData)
UINT32 EFIAPI PciCf8And32 (IN UINTN Address, IN UINT32 AndData)
UINT32 EFIAPI PciCf8AndThenOr32 (IN UINTN Address, IN UINT32 AndData, IN UINT32 OrData)
UINT32 EFIAPI PciCf8BitFieldRead32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
UINT32 EFIAPI PciCf8BitFieldWrite32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value)
UINT32 EFIAPI PciCf8BitFieldOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 OrData)
UINT32 EFIAPI PciCf8BitFieldAnd32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData)
UINT32 EFIAPI PciCf8BitFieldAndThenOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData, IN UINT32 OrData)
UINTN EFIAPI PciCf8ReadBuffer (IN UINTN StartAddress, IN UINTN Size, OUT VOID *Buffer)
UINTN EFIAPI PciCf8WriteBuffer (IN UINTN StartAddress, IN UINTN Size, IN VOID *Buffer)

Detailed Description

Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.

This library is identical to the PCI Library, except the access method for performing PCI configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows access to PCI Segment #0.

Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.


Define Documentation

#define PCI_CF8_LIB_ADDRESS ( Bus,
Device,
Function,
Offset   )     (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))

Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an address that can be passed to the PCI Library functions.

Computes an address that is compatible with the PCI Library functions. The unused upper bits of Bus, Device, Function and Register are stripped prior to the generation of the address.

Parameters:
Bus PCI Bus number. Range 0..255.
Device PCI Device number. Range 0..31.
Function PCI Function number. Range 0..7.
Register PCI Register number. Range 0..255.
Returns:
The encode PCI address.


Function Documentation

UINT16 EFIAPI PciCf8And16 ( IN UINTN  Address,
IN UINT16  AndData 
)

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoAnd16(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciAnd16().

UINT32 EFIAPI PciCf8And32 ( IN UINTN  Address,
IN UINT32  AndData 
)

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoAnd32(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciAnd32().

UINT8 EFIAPI PciCf8And8 ( IN UINTN  Address,
IN UINT8  AndData 
)

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoAnd8(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciAnd8().

UINT16 EFIAPI PciCf8AndThenOr16 ( IN UINTN  Address,
IN UINT16  AndData,
IN UINT16  OrData 
)

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoAndThenOr16(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciAndThenOr16().

UINT32 EFIAPI PciCf8AndThenOr32 ( IN UINTN  Address,
IN UINT32  AndData,
IN UINT32  OrData 
)

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoAndThenOr32(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciAndThenOr32().

UINT8 EFIAPI PciCf8AndThenOr8 ( IN UINTN  Address,
IN UINT8  AndData,
IN UINT8  OrData 
)

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoAndThenOr8(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciAndThenOr8().

UINT16 EFIAPI PciCf8BitFieldAnd16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  AndData 
)

Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 16-bit register.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 16-bit register.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldAnd16(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldAnd16().

UINT32 EFIAPI PciCf8BitFieldAnd32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  AndData 
)

Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldAnd32(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldAnd32().

UINT8 EFIAPI PciCf8BitFieldAnd8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  AndData 
)

Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldAnd8(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldAnd8().

UINT16 EFIAPI PciCf8BitFieldAndThenOr16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  AndData,
IN UINT16  OrData 
)

Reads a bit field in a 16-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldAndThenOr16(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldAndThenOr16().

UINT32 EFIAPI PciCf8BitFieldAndThenOr32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  AndData,
IN UINT32  OrData 
)

Reads a bit field in a 32-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldAndThenOr32(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldAndThenOr32().

UINT8 EFIAPI PciCf8BitFieldAndThenOr8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  AndData,
IN UINT8  OrData 
)

Reads a bit field in an 8-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldAndThenOr8(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldAndThenOr8().

UINT16 EFIAPI PciCf8BitFieldOr16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  OrData 
)

Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldOr16(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldOr16().

UINT32 EFIAPI PciCf8BitFieldOr32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  OrData 
)

Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldOr32(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldOr32().

UINT8 EFIAPI PciCf8BitFieldOr8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  OrData 
)

Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldOr8(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldOr8().

UINT16 EFIAPI PciCf8BitFieldRead16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit 
)

Reads a bit field of a PCI configuration register.

Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Returns:
The value of the bit field read from the PCI configuration register.
Reads a bit field of a PCI configuration register.

Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address The PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Returns:
The value of the bit field read from the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldRead16(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldRead16().

UINT32 EFIAPI PciCf8BitFieldRead32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit 
)

Reads a bit field of a PCI configuration register.

Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Returns:
The value of the bit field read from the PCI configuration register.
Reads a bit field of a PCI configuration register.

Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address The PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Returns:
The value of the bit field read from the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldRead32(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldRead32().

UINT8 EFIAPI PciCf8BitFieldRead8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit 
)

Reads a bit field of a PCI configuration register.

Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Returns:
The value of the bit field read from the PCI configuration register.
Reads a bit field of a PCI configuration register.

Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address The PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Returns:
The value of the bit field read from the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldRead8(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldRead8().

UINT16 EFIAPI PciCf8BitFieldWrite16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  Value 
)

Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Value New value of the bit field.
Returns:
The value written back to the PCI configuration register.
Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Value The new value of the bit field.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldWrite16(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldWrite16().

UINT32 EFIAPI PciCf8BitFieldWrite32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  Value 
)

Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Value New value of the bit field.
Returns:
The value written back to the PCI configuration register.
Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Value The new value of the bit field.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldWrite32(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldWrite32().

UINT8 EFIAPI PciCf8BitFieldWrite8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  Value 
)

Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Value New value of the bit field.
Returns:
The value written back to the PCI configuration register.
Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Value The new value of the bit field.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoBitFieldWrite8(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciBitFieldWrite8().

UINT16 EFIAPI PciCf8Or16 ( IN UINTN  Address,
IN UINT16  OrData 
)

Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoOr16(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciOr16().

UINT32 EFIAPI PciCf8Or32 ( IN UINTN  Address,
IN UINT32  OrData 
)

Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoOr32(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciOr32().

UINT8 EFIAPI PciCf8Or8 ( IN UINTN  Address,
IN UINT8  OrData 
)

Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoOr8(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciOr8().

UINT16 EFIAPI PciCf8Read16 ( IN UINTN  Address  ) 

Reads a 16-bit PCI configuration register.

Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.
Reads a 16-bit PCI configuration register.

Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoRead16(), IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciCf8ReadBuffer(), and PciRead16().

UINT32 EFIAPI PciCf8Read32 ( IN UINTN  Address  ) 

Reads a 32-bit PCI configuration register.

Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.
Reads a 32-bit PCI configuration register.

Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciCf8ReadBuffer(), and PciRead32().

UINT8 EFIAPI PciCf8Read8 ( IN UINTN  Address  ) 

Reads an 8-bit PCI configuration register.

Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.
Reads an 8-bit PCI configuration register.

Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoRead32(), IoRead8(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciCf8ReadBuffer(), and PciRead8().

UINTN EFIAPI PciCf8ReadBuffer ( IN UINTN  StartAddress,
IN UINTN  Size,
OUT VOID *  Buffer 
)

Reads a range of PCI configuration registers into a caller supplied buffer.

Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If the register specified by StartAddress >= 0x100, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress Starting address that encodes the PCI Bus, Device, Function and Register.
Size Size in bytes of the transfer.
Buffer Pointer to a buffer receiving the data read.
Returns:
Size read from StartAddress.
Reads a range of PCI configuration registers into a caller supplied buffer.

Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If the register specified by StartAddress >= 0x100, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress The starting address that encodes the PCI Bus, Device, Function and Register.
Size The size in bytes of the transfer.
Buffer The pointer to a buffer receiving the data read.
Returns:
Size read from StartAddress.

References ASSERT, ASSERT_INVALID_PCI_ADDRESS, NULL, PciCf8Read16(), PciCf8Read32(), PciCf8Read8(), WriteUnaligned16(), and WriteUnaligned32().

Referenced by PciReadBuffer().

RETURN_STATUS EFIAPI PciCf8RegisterForRuntimeAccess ( IN UINTN  Address  ) 

Registers a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap().

Registers the PCI device specified by Address so all the PCI configuration registers associated with that PCI device may be accessed after SetVirtualAddressMap() is called.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Return values:
RETURN_SUCCESS The PCI device was registered for runtime access.
RETURN_UNSUPPORTED An attempt was made to call this function after ExitBootServices().
RETURN_UNSUPPORTED The resources required to access the PCI device at runtime could not be mapped.
RETURN_OUT_OF_RESOURCES There are not enough resources available to complete the registration.
Registers a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap().

Registers the PCI device specified by Address so all the PCI configuration registers associated with that PCI device may be accessed after SetVirtualAddressMap() is called.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Return values:
RETURN_SUCCESS The PCI device was registered for runtime access.
RETURN_UNSUPPORTED An attempt was made to call this function after ExitBootServices().
RETURN_UNSUPPORTED The resources required to access the PCI device at runtime could not be mapped.
RETURN_OUT_OF_RESOURCES There are not enough resources available to complete the registration.

References ASSERT_INVALID_PCI_ADDRESS, and RETURN_SUCCESS.

Referenced by PciRegisterForRuntimeAccess().

UINT16 EFIAPI PciCf8Write16 ( IN UINTN  Address,
IN UINT16  Value 
)

Writes a 16-bit PCI configuration register.

Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.
Writes a 16-bit PCI configuration register.

Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoRead32(), IoWrite16(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciCf8WriteBuffer(), and PciWrite16().

UINT32 EFIAPI PciCf8Write32 ( IN UINTN  Address,
IN UINT32  Value 
)

Writes a 32-bit PCI configuration register.

Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.
Writes a 32-bit PCI configuration register.

Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoRead32(), IoWrite32(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciCf8WriteBuffer(), and PciWrite32().

UINT8 EFIAPI PciCf8Write8 ( IN UINTN  Address,
IN UINT8  Value 
)

Writes an 8-bit PCI configuration register.

Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.
Writes an 8-bit PCI configuration register.

Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If the register specified by Address >= 0x100, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, IoRead32(), IoWrite32(), IoWrite8(), PCI_CONFIGURATION_ADDRESS_PORT, PCI_CONFIGURATION_DATA_PORT, PCI_TO_CF8_ADDRESS, SaveAndDisableInterrupts(), and SetInterruptState().

Referenced by PciCf8WriteBuffer(), and PciWrite8().

UINTN EFIAPI PciCf8WriteBuffer ( IN UINTN  StartAddress,
IN UINTN  Size,
IN VOID *  Buffer 
)

Copies the data in a caller supplied buffer to a specified range of PCI configuration space.

Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If the register specified by StartAddress >= 0x100, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress Starting address that encodes the PCI Bus, Device, Function and Register.
Size Size in bytes of the transfer.
Buffer Pointer to a buffer containing the data to write.
Returns:
Size written to StartAddress.
Copies the data in a caller supplied buffer to a specified range of PCI configuration space.

Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If the register specified by StartAddress >= 0x100, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress The starting address that encodes the PCI Bus, Device, Function and Register.
Size The size in bytes of the transfer.
Buffer The pointer to a buffer containing the data to write.
Returns:
Size written to StartAddress.

References ASSERT, ASSERT_INVALID_PCI_ADDRESS, NULL, PciCf8Write16(), PciCf8Write32(), PciCf8Write8(), ReadUnaligned16(), and ReadUnaligned32().

Referenced by PciWriteBuffer().


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