Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define AR_VALID_BIT_MASK 0x8 |
#define BR_VALID_BIT_MASK 0x2 |
#define CHECK_INFO_VALID_BIT_MASK 0x1 |
#define CPU_INFO_VALID_BIT_MASK 0x1000000 |
#define CR_VALID_BIT_MASK 0x4 |
#define EFI_SAL_CACHE_FLUSH 0x01000008 |
Flush the instruction or data caches.
#define EFI_SAL_CACHE_INIT 0x01000009 |
Initialize the instruction and data caches.
#define EFI_SAL_CLEAR_STATE_INFO 0x01000003 |
Clear Machine State information.
#define EFI_SAL_CMC_STATE_INFO 0x2 |
#define EFI_SAL_CP_STATE_INFO 0x3 |
#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0 |
#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3) |
Call completed without error.
#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) |
#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00 |
#define EFI_SAL_FIT_PAL_A_TYPE 0x0F |
#define EFI_SAL_FIT_PAL_B_TYPE 0x01 |
#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) |
#define EFI_SAL_FIT_PALB_TYPE 01 |
#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10 |
#define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E |
#define EFI_SAL_FIT_UNUSED_TYPE 0x7F |
#define EFI_SAL_FLUSH_BOTH_CACHE 0x03 |
#define EFI_SAL_FLUSH_D_CACHE 0x02 |
#define EFI_SAL_FLUSH_I_CACHE 0x01 |
#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04 |
#define EFI_SAL_FREQ_BASE 0x01000012 |
Return the base frequency of the platform.
#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff |
#define EFI_SAL_GET_STATE_INFO 0x01000001 |
Return Machine State information obtained by SAL.
#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002 |
Obtain size of Machine State information.
#define EFI_SAL_INIT_STATE_INFO 0x1 |
#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2) |
Invalid Argument.
#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021 |
#define EFI_SAL_MC_RENDEZ 0x01000004 |
Cause the processor to go into a spin loop within SAL.
#define EFI_SAL_MC_SET_CPE_PARAM 0x3 |
#define EFI_SAL_MC_SET_INTR_PARAM 0x1 |
#define EFI_SAL_MC_SET_MEM_PARAM 0x2 |
#define EFI_SAL_MC_SET_PARAMS 0x01000005 |
Register the machine check interface layer with SAL.
#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1 |
#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2 |
#define EFI_SAL_MCA_STATE_INFO 0x0 |
#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3) |
More information is available for retrieval.
#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5) |
No information available.
#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9) |
Scratch buffer required.
#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1) |
Not implemented.
#define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1) |
Call completed without error, but some information was lost due to overflow.
#define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0 |
#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4 |
#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1 |
#define EFI_SAL_PCI_CONFIG_READ 0x01000010 |
Read from the PCI configuration space.
#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2 |
#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011 |
Write to the PCI configuration space.
#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1 |
#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013 |
Returns information on the physical processor mapping within the platform.
#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1 |
#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2 |
#define EFI_SAL_REGISTER_PAL_ADDR 0x0 |
#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006 |
Register the physical addresses of locations needed by SAL.
#define EFI_SAL_REVISION 0x0320 |
#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2 |
#define EFI_SAL_SET_INIT_VECTOR 0x1 |
#define EFI_SAL_SET_MCA_VECTOR 0x0 |
#define EFI_SAL_SET_VECTORS 0x01000000 |
Register software code locations with SAL.
#define EFI_SAL_ST_AP_WAKEUP 5 |
#define EFI_SAL_ST_AP_WAKEUP_SIZE 16 |
#define EFI_SAL_ST_ENTRY_POINT 0 |
#define EFI_SAL_ST_ENTRY_POINT_SIZE 48 |
#define EFI_SAL_ST_HEADER_SIGNATURE "SST_" |
#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1 |
#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32 |
#define EFI_SAL_ST_PLATFORM_FEATURES 2 |
#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16 |
#define EFI_SAL_ST_PTC 4 |
#define EFI_SAL_ST_PTC_SIZE 16 |
#define EFI_SAL_ST_TR_USAGE 3 |
#define EFI_SAL_ST_TR_USAGE_DATA 01 |
#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00 |
#define EFI_SAL_ST_TR_USAGE_SIZE 32 |
#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0) |
Call completed without error.
#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1) |
#define EFI_SAL_UPDATE_PAL 0x01000020 |
Update the contents of firmware blocks.
#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2) |
#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3) |
#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13) |
#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11) |
#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12) |
#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4) |
#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10) |
#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4) |
Virtual address not registered.
#define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2) |
Call completed without error; effect a warm boot of the system to complete the update.
#define FR_VALID_BIT_MASK 0x20 |
#define MEMORY_ADDR_BIT_MASK 0x4 |
#define MEMORY_BANK_VALID_BIT_MASK 0x40 |
#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400 |
#define MEMORY_CARD_VALID_BIT_MASK 0x10 |
#define MEMORY_COLUMN_VALID_BIT_MASK 0x200 |
#define MEMORY_DEVICE_VALID_BIT_MASK 0x80 |
#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1 |
#define MEMORY_MODULE_VALID_BIT_MASK 0x20 |
#define MEMORY_NODE_VALID_BIT_MASK 0x8 |
#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2 |
#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000 |
#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000 |
#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000 |
#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800 |
#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000 |
#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000 |
#define MEMORY_ROW_VALID_BIT_MASK 0x100 |
#define MIN_STATE_VALID_BIT_MASK 0x1 |
#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8 |
#define PCI_BUS_CMD_VALID_BIT_MASK 0x20 |
#define PCI_BUS_DATA_VALID_BIT_MASK 0x10 |
#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1 |
#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2 |
#define PCI_BUS_ID_VALID_BIT_MASK 0x4 |
#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400 |
#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200 |
#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40 |
#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80 |
#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100 |
#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1 |
#define PCI_COMP_INFO_VALID_BIT_MASK 0x2 |
#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8 |
#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4 |
#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20 |
#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10 |
#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1 |
#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40 |
#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80 |
#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20 |
#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2 |
#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4 |
#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10 |
#define PLATFORM_TARGET_VALID_BIT_MASK 0x8 |
#define PRECISE_IP_VALID_BIT_MASK 0x10 |
#define PROC_CR_LID_VALID_BIT_MASK 0x4 |
#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1 |
#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2 |
#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8 |
#define REQUESTOR_ID_VALID_BIT_MASK 0x2 |
#define RESPONDER_ID_VALID_BIT_MASK 0x4 |
#define RR_VALID_BIT_MASK 0x10 |
#define SAL_MEMORY_ERROR_RECORD_INFO |
Value:
{ \ 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ }
#define SAL_PCI_BUS_ERROR_RECORD_INFO |
Value:
{ \ 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ }
#define SAL_PCI_COMP_ERROR_RECORD_INFO |
Value:
{ \ 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ }
#define SAL_PLAT_FEAT_BUS_LOCK 0x01 |
#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02 |
#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04 |
#define SAL_PLATFORM_ERROR_RECORD_INFO |
Value:
{ \ 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ }
#define SAL_PROCESSOR_ERROR_RECORD_INFO |
Value:
{ \ 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ }
#define SAL_SEL_DEVICE_ERROR_RECORD_INFO |
Value:
{ \ 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ }
#define SAL_SMBIOS_ERROR_RECORD_INFO |
Value:
{ \ 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ }
#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80; |
#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100; |
#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200; |
#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40; |
#define SEL_EVM_REV_VALID_BIT_MASK 0x8; |
#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4; |
#define SEL_RECORD_ID_VALID_BIT_MASK 0x1; |
#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2; |
#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20; |
#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10; |
#define SMBIOS_DATA_VALID_BIT_MASK 0x8 |
#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1 |
#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2 |
#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4 |
#define TARGER_ID_VALID_BIT_MASK 0x8 |
typedef INTN EFI_SAL_STATUS |
SAL return status type
typedef SAL_RETURN_REGS(EFIAPI * SAL_PROC)(IN UINT64 FunctionId, IN UINT64 Arg1, IN UINT64 Arg2, IN UINT64 Arg3, IN UINT64 Arg4, IN UINT64 Arg5, IN UINT64 Arg6, IN UINT64 Arg7) |
Prototype of SAL procedures.
FunctionId | Functional identifier. The upper 32 bits are ignored and only the lower 32 bits are used. The following functional identifiers are defined: 0x01XXXXXX - Architected SAL functional group. 0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range. 0x04XXXXXX to 0xFFFFFFFF - Reserved. | |
Arg1 | The first parameter of the architected/OEM specific SAL functions. | |
Arg2 | The second parameter of the architected/OEM specific SAL functions. | |
Arg3 | The third parameter passed to the ESAL function based. | |
Arg4 | The fourth parameter passed to the ESAL function based. | |
Arg5 | The fifth parameter passed to the ESAL function based. | |
Arg6 | The sixth parameter passed to the ESAL function. | |
Arg7 | The seventh parameter passed to the ESAL function based. |
typedef struct _SAL_UPDATE_PAL_INFO_BLOCK SAL_UPDATE_PAL_INFO_BLOCK |
Data structure pointed by the parameter param_buf. It is a 16-byte aligned data structure in memory with a length of 32 bytes that describes the new firmware. This information is organized in the form of a linked list with each element describing one firmware component.