MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c File Reference


Functions

EFI_STATUS EFIAPI PciSegmentLibConstructor (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
EFI_STATUS EFIAPI PciSegmentLibDestructor (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOLPciSegmentLibSearchForRootBridge (IN UINT64 Address)
UINT32 DxePciSegmentLibPciRootBridgeIoReadWorker (IN UINT64 Address, IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width)
UINT32 DxePciSegmentLibPciRootBridgeIoWriteWorker (IN UINT64 Address, IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, IN UINT32 Data)
RETURN_STATUS EFIAPI PciSegmentRegisterForRuntimeAccess (IN UINTN Address)
UINT8 EFIAPI PciSegmentRead8 (IN UINT64 Address)
UINT8 EFIAPI PciSegmentWrite8 (IN UINT64 Address, IN UINT8 Value)
UINT8 EFIAPI PciSegmentOr8 (IN UINT64 Address, IN UINT8 OrData)
UINT8 EFIAPI PciSegmentAnd8 (IN UINT64 Address, IN UINT8 AndData)
UINT8 EFIAPI PciSegmentAndThenOr8 (IN UINT64 Address, IN UINT8 AndData, IN UINT8 OrData)
UINT8 EFIAPI PciSegmentBitFieldRead8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit)
UINT8 EFIAPI PciSegmentBitFieldWrite8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 Value)
UINT8 EFIAPI PciSegmentBitFieldOr8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 OrData)
UINT8 EFIAPI PciSegmentBitFieldAnd8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData)
UINT8 EFIAPI PciSegmentBitFieldAndThenOr8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData, IN UINT8 OrData)
UINT16 EFIAPI PciSegmentRead16 (IN UINT64 Address)
UINT16 EFIAPI PciSegmentWrite16 (IN UINT64 Address, IN UINT16 Value)
UINT16 EFIAPI PciSegmentOr16 (IN UINT64 Address, IN UINT16 OrData)
UINT16 EFIAPI PciSegmentAnd16 (IN UINT64 Address, IN UINT16 AndData)
UINT16 EFIAPI PciSegmentAndThenOr16 (IN UINT64 Address, IN UINT16 AndData, IN UINT16 OrData)
UINT16 EFIAPI PciSegmentBitFieldRead16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit)
UINT16 EFIAPI PciSegmentBitFieldWrite16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 Value)
UINT16 EFIAPI PciSegmentBitFieldOr16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 OrData)
UINT16 EFIAPI PciSegmentBitFieldAnd16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData)
UINT16 EFIAPI PciSegmentBitFieldAndThenOr16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData, IN UINT16 OrData)
UINT32 EFIAPI PciSegmentRead32 (IN UINT64 Address)
UINT32 EFIAPI PciSegmentWrite32 (IN UINT64 Address, IN UINT32 Value)
UINT32 EFIAPI PciSegmentOr32 (IN UINT64 Address, IN UINT32 OrData)
UINT32 EFIAPI PciSegmentAnd32 (IN UINT64 Address, IN UINT32 AndData)
UINT32 EFIAPI PciSegmentAndThenOr32 (IN UINT64 Address, IN UINT32 AndData, IN UINT32 OrData)
UINT32 EFIAPI PciSegmentBitFieldRead32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit)
UINT32 EFIAPI PciSegmentBitFieldWrite32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value)
UINT32 EFIAPI PciSegmentBitFieldOr32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 OrData)
UINT32 EFIAPI PciSegmentBitFieldAnd32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData)
UINT32 EFIAPI PciSegmentBitFieldAndThenOr32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData, IN UINT32 OrData)
UINTN EFIAPI PciSegmentReadBuffer (IN UINT64 StartAddress, IN UINTN Size, OUT VOID *Buffer)
UINTN EFIAPI PciSegmentWriteBuffer (IN UINT64 StartAddress, IN UINTN Size, IN VOID *Buffer)

Variables

PCI_ROOT_BRIDGE_DATAmPciRootBridgeData = NULL
UINTN mNumberOfPciRootBridges = 0

Detailed Description

PCI Segment Library implementation using PCI Root Bridge I/O Protocol.

Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.


Function Documentation

UINT32 DxePciSegmentLibPciRootBridgeIoReadWorker ( IN UINT64  Address,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width 
)

Internal worker function to read a PCI configuration register.

This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service. It reads and returns the PCI configuration register specified by Address, the width of data is specified by Width.

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Width Width of data to read
Returns:
The value read from the PCI configuration register.

References ASSERT, NULL, _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Pci, PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS, PciSegmentLibSearchForRootBridge(), and EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS::Read.

Referenced by PciSegmentRead16(), PciSegmentRead32(), and PciSegmentRead8().

UINT32 DxePciSegmentLibPciRootBridgeIoWriteWorker ( IN UINT64  Address,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
IN UINT32  Data 
)

Internal worker function to writes a PCI configuration register.

This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service. It writes the PCI configuration register specified by Address with the value specified by Data. The width of data is specifed by Width. Data is returned.

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Width Width of data to write
Data The value to write.
Returns:
The value written to the PCI configuration register.

References ASSERT, NULL, _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Pci, PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS, PciSegmentLibSearchForRootBridge(), and EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS::Write.

Referenced by PciSegmentWrite16(), PciSegmentWrite32(), and PciSegmentWrite8().

UINT16 EFIAPI PciSegmentAnd16 ( IN UINT64  Address,
IN UINT16  AndData 
)

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written to the PCI configuration register.

References PciSegmentRead16(), and PciSegmentWrite16().

UINT32 EFIAPI PciSegmentAnd32 ( IN UINT64  Address,
IN UINT32  AndData 
)

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written to the PCI configuration register.

References PciSegmentRead32(), and PciSegmentWrite32().

UINT8 EFIAPI PciSegmentAnd8 ( IN UINT64  Address,
IN UINT8  AndData 
)

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. If any reserved bits in Address are set, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written to the PCI configuration register.

References PciSegmentRead8(), and PciSegmentWrite8().

UINT16 EFIAPI PciSegmentAndThenOr16 ( IN UINT64  Address,
IN UINT16  AndData,
IN UINT16  OrData 
)

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written to the PCI configuration register.

References PciSegmentRead16(), and PciSegmentWrite16().

UINT32 EFIAPI PciSegmentAndThenOr32 ( IN UINT64  Address,
IN UINT32  AndData,
IN UINT32  OrData 
)

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written to the PCI configuration register.

References PciSegmentRead32(), and PciSegmentWrite32().

UINT8 EFIAPI PciSegmentAndThenOr8 ( IN UINT64  Address,
IN UINT8  AndData,
IN UINT8  OrData 
)

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written to the PCI configuration register.

References PciSegmentRead8(), and PciSegmentWrite8().

UINT16 EFIAPI PciSegmentBitFieldAnd16 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  AndData 
)

Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
StartBit The ordinal of the least significant bit in the bit field. The ordinal of the least significant bit in a byte is bit 0.
EndBit The ordinal of the most significant bit in the bit field. The ordinal of the most significant bit in a byte is bit 7.
AndData The value to AND with the read value from the PCI configuration register.
Returns:
The value written to the PCI configuration register.

References BitFieldAnd16(), PciSegmentRead16(), and PciSegmentWrite16().

UINT32 EFIAPI PciSegmentBitFieldAnd32 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  AndData 
)

Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped. If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldAnd32(), PciSegmentRead32(), and PciSegmentWrite32().

UINT8 EFIAPI PciSegmentBitFieldAnd8 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  AndData 
)

Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldAnd8(), PciSegmentRead8(), and PciSegmentWrite8().

UINT16 EFIAPI PciSegmentBitFieldAndThenOr16 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  AndData,
IN UINT16  OrData 
)

Reads a bit field in a 16-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References BitFieldAndThenOr16(), PciSegmentRead16(), and PciSegmentWrite16().

UINT32 EFIAPI PciSegmentBitFieldAndThenOr32 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  AndData,
IN UINT32  OrData 
)

Reads a bit field in a 32-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References BitFieldAndThenOr32(), PciSegmentRead32(), and PciSegmentWrite32().

UINT8 EFIAPI PciSegmentBitFieldAndThenOr8 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  AndData,
IN UINT8  OrData 
)

Reads a bit field in an 8-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References BitFieldAndThenOr8(), PciSegmentRead8(), and PciSegmentWrite8().

UINT16 EFIAPI PciSegmentBitFieldOr16 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  OrData 
)

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldOr16(), PciSegmentRead16(), and PciSegmentWrite16().

UINT32 EFIAPI PciSegmentBitFieldOr32 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  OrData 
)

Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldOr32(), PciSegmentRead32(), and PciSegmentWrite32().

UINT8 EFIAPI PciSegmentBitFieldOr8 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  OrData 
)

Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldOr8(), PciSegmentRead8(), and PciSegmentWrite8().

UINT16 EFIAPI PciSegmentBitFieldRead16 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit 
)

Reads a bit field of a PCI configuration register.

Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address The PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Returns:
The value of the bit field read from the PCI configuration register.

References BitFieldRead16(), and PciSegmentRead16().

UINT32 EFIAPI PciSegmentBitFieldRead32 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit 
)

Reads a bit field of a PCI configuration register.

Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address The PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Returns:
The value of the bit field read from the PCI configuration register.

References BitFieldRead32(), and PciSegmentRead32().

UINT8 EFIAPI PciSegmentBitFieldRead8 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit 
)

Reads a bit field of a PCI configuration register.

Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address The PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Returns:
The value of the bit field read from the PCI configuration register.

References BitFieldRead8(), and PciSegmentRead8().

UINT16 EFIAPI PciSegmentBitFieldWrite16 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  Value 
)

Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Value The new value of the bit field.
Returns:
The value written back to the PCI configuration register.

References BitFieldWrite16(), PciSegmentRead16(), and PciSegmentWrite16().

UINT32 EFIAPI PciSegmentBitFieldWrite32 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  Value 
)

Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Value The new value of the bit field.
Returns:
The value written back to the PCI configuration register.

References BitFieldWrite32(), PciSegmentRead32(), and PciSegmentWrite32().

UINT8 EFIAPI PciSegmentBitFieldWrite8 ( IN UINT64  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  Value 
)

Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.

If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Value The new value of the bit field.
Returns:
The value written back to the PCI configuration register.

References BitFieldWrite8(), PciSegmentRead8(), and PciSegmentWrite8().

EFI_STATUS EFIAPI PciSegmentLibConstructor ( IN EFI_HANDLE  ImageHandle,
IN EFI_SYSTEM_TABLE SystemTable 
)

The constructor function caches data of PCI Root Bridge I/O Protocol instances.

The constructor function locates PCI Root Bridge I/O protocol instances, and caches the protocol instances, together with their segment numbers and bus ranges. It will ASSERT() if that related operation fails and it will always return EFI_SUCCESS.

Parameters:
ImageHandle The firmware allocated handle for the EFI image.
SystemTable A pointer to the EFI System Table.
Return values:
EFI_SUCCESS The constructor always returns EFI_SUCCESS.

References ACPI_ADDRESS_SPACE_TYPE_BUS, ACPI_END_TAG_DESCRIPTOR, AllocatePool(), ASSERT, ASSERT_EFI_ERROR, ByProtocol, EFI_SUCCESS, FreePool(), gBS, gEfiPciRootBridgeIoProtocolGuid, EFI_BOOT_SERVICES::HandleProtocol, EFI_BOOT_SERVICES::LocateHandleBuffer, PCI_ROOT_BRIDGE_DATA::MaxBusNumber, PCI_ROOT_BRIDGE_DATA::MinBusNumber, mNumberOfPciRootBridges, NULL, PCI_ROOT_BRIDGE_DATA::PciRootBridgeIo, PCI_ROOT_BRIDGE_DATA::SegmentNumber, and VOID.

EFI_STATUS EFIAPI PciSegmentLibDestructor ( IN EFI_HANDLE  ImageHandle,
IN EFI_SYSTEM_TABLE SystemTable 
)

The destructor function frees memory allocated by constructor.

The destructor function frees memory for data of protocol instances allocated by constructor. It will ASSERT() if that related operation fails and it will always return EFI_SUCCESS.

Parameters:
ImageHandle The firmware allocated handle for the EFI image.
SystemTable A pointer to the EFI System Table.
Return values:
EFI_SUCCESS The constructor always returns EFI_SUCCESS.

References EFI_SUCCESS, and FreePool().

EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL* PciSegmentLibSearchForRootBridge ( IN UINT64  Address  ) 

According to address, search for the corresponding PCI Root Bridge I/O Protocol instance.

This internal function extracts segment number and bus number data from address, and retrieves the corresponding PCI Root Bridge I/O Protocol instance.

Parameters:
Address The address that encodes the Segment, PCI Bus, Device, Function and Register.
Returns:
The address for PCI Root Bridge I/O Protocol.

References BitFieldRead64(), mNumberOfPciRootBridges, NULL, and PCI_ROOT_BRIDGE_DATA::PciRootBridgeIo.

Referenced by DxePciSegmentLibPciRootBridgeIoReadWorker(), and DxePciSegmentLibPciRootBridgeIoWriteWorker().

UINT16 EFIAPI PciSegmentOr16 ( IN UINT64  Address,
IN UINT16  OrData 
)

Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References PciSegmentRead16(), and PciSegmentWrite16().

UINT32 EFIAPI PciSegmentOr32 ( IN UINT64  Address,
IN UINT32  OrData 
)

Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written to the PCI configuration register.

References PciSegmentRead32(), and PciSegmentWrite32().

UINT8 EFIAPI PciSegmentOr8 ( IN UINT64  Address,
IN UINT8  OrData 
)

Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written to the PCI configuration register.

References PciSegmentRead8(), and PciSegmentWrite8().

UINT16 EFIAPI PciSegmentRead16 ( IN UINT64  Address  ) 

Reads a 16-bit PCI configuration register.

Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
Returns:
The 16-bit PCI configuration register specified by Address.

References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, DxePciSegmentLibPciRootBridgeIoReadWorker(), and EfiPciWidthUint16.

Referenced by PciSegmentAnd16(), PciSegmentAndThenOr16(), PciSegmentBitFieldAnd16(), PciSegmentBitFieldAndThenOr16(), PciSegmentBitFieldOr16(), PciSegmentBitFieldRead16(), PciSegmentBitFieldWrite16(), PciSegmentOr16(), and PciSegmentReadBuffer().

UINT32 EFIAPI PciSegmentRead32 ( IN UINT64  Address  ) 

Reads a 32-bit PCI configuration register.

Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
Returns:
The 32-bit PCI configuration register specified by Address.

References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, DxePciSegmentLibPciRootBridgeIoReadWorker(), and EfiPciWidthUint32.

Referenced by PciSegmentAnd32(), PciSegmentAndThenOr32(), PciSegmentBitFieldAnd32(), PciSegmentBitFieldAndThenOr32(), PciSegmentBitFieldOr32(), PciSegmentBitFieldRead32(), PciSegmentBitFieldWrite32(), PciSegmentOr32(), and PciSegmentReadBuffer().

UINT8 EFIAPI PciSegmentRead8 ( IN UINT64  Address  ) 

Reads an 8-bit PCI configuration register.

Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
Returns:
The 8-bit PCI configuration register specified by Address.

References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, DxePciSegmentLibPciRootBridgeIoReadWorker(), and EfiPciWidthUint8.

Referenced by PciSegmentAnd8(), PciSegmentAndThenOr8(), PciSegmentBitFieldAnd8(), PciSegmentBitFieldAndThenOr8(), PciSegmentBitFieldOr8(), PciSegmentBitFieldRead8(), PciSegmentBitFieldWrite8(), PciSegmentOr8(), and PciSegmentReadBuffer().

UINTN EFIAPI PciSegmentReadBuffer ( IN UINT64  StartAddress,
IN UINTN  Size,
OUT VOID *  Buffer 
)

Reads a range of PCI configuration registers into a caller supplied buffer.

Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.

If any reserved bits in StartAddress are set, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress The starting address that encodes the PCI Segment, Bus, Device, Function and Register.
Size The size in bytes of the transfer.
Buffer The pointer to a buffer receiving the data read.
Returns:
Size

References ASSERT, ASSERT_INVALID_PCI_SEGMENT_ADDRESS, BIT0, BIT1, NULL, PciSegmentRead16(), PciSegmentRead32(), PciSegmentRead8(), WriteUnaligned16(), and WriteUnaligned32().

RETURN_STATUS EFIAPI PciSegmentRegisterForRuntimeAccess ( IN UINTN  Address  ) 

Register a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap().

If any reserved bits in Address are set, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Return values:
RETURN_SUCCESS The PCI device was registered for runtime access.
RETURN_UNSUPPORTED An attempt was made to call this function after ExitBootServices().
RETURN_UNSUPPORTED The resources required to access the PCI device at runtime could not be mapped.
RETURN_OUT_OF_RESOURCES There are not enough resources available to complete the registration.

References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, and RETURN_UNSUPPORTED.

UINT16 EFIAPI PciSegmentWrite16 ( IN UINT64  Address,
IN UINT16  Value 
)

Writes a 16-bit PCI configuration register.

Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
Value The value to write.
Returns:
The parameter of Value.

References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, DxePciSegmentLibPciRootBridgeIoWriteWorker(), and EfiPciWidthUint16.

Referenced by PciSegmentAnd16(), PciSegmentAndThenOr16(), PciSegmentBitFieldAnd16(), PciSegmentBitFieldAndThenOr16(), PciSegmentBitFieldOr16(), PciSegmentBitFieldWrite16(), PciSegmentOr16(), and PciSegmentWriteBuffer().

UINT32 EFIAPI PciSegmentWrite32 ( IN UINT64  Address,
IN UINT32  Value 
)

Writes a 32-bit PCI configuration register.

Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
Value The value to write.
Returns:
The parameter of Value.

References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, DxePciSegmentLibPciRootBridgeIoWriteWorker(), and EfiPciWidthUint32.

Referenced by PciSegmentAnd32(), PciSegmentAndThenOr32(), PciSegmentBitFieldAnd32(), PciSegmentBitFieldAndThenOr32(), PciSegmentBitFieldOr32(), PciSegmentBitFieldWrite32(), PciSegmentOr32(), and PciSegmentWriteBuffer().

UINT8 EFIAPI PciSegmentWrite8 ( IN UINT64  Address,
IN UINT8  Value 
)

Writes an 8-bit PCI configuration register.

Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If any reserved bits in Address are set, then ASSERT().

Parameters:
Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.

References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, DxePciSegmentLibPciRootBridgeIoWriteWorker(), and EfiPciWidthUint8.

Referenced by PciSegmentAnd8(), PciSegmentAndThenOr8(), PciSegmentBitFieldAnd8(), PciSegmentBitFieldAndThenOr8(), PciSegmentBitFieldOr8(), PciSegmentBitFieldWrite8(), PciSegmentOr8(), and PciSegmentWriteBuffer().

UINTN EFIAPI PciSegmentWriteBuffer ( IN UINT64  StartAddress,
IN UINTN  Size,
IN VOID *  Buffer 
)

Copies the data in a caller supplied buffer to a specified range of PCI configuration space.

Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.

If any reserved bits in StartAddress are set, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress The starting address that encodes the PCI Segment, Bus, Device, Function and Register.
Size The size in bytes of the transfer.
Buffer The pointer to a buffer containing the data to write.
Returns:
The parameter of Size.

References ASSERT, ASSERT_INVALID_PCI_SEGMENT_ADDRESS, BIT0, BIT1, NULL, PciSegmentWrite16(), PciSegmentWrite32(), PciSegmentWrite8(), ReadUnaligned16(), and ReadUnaligned32().


Variable Documentation


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